`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:33:45 02/19/2014 
// Design Name: 
// Module Name:    top_level 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top_level(
    input cam_clk,
	 input clk_in,
    input frame_valid,
    input line_valid,
    input [7:0] pixel_data,
    output wire [3:0] ext_tmds,
    output wire [3:0] ext_tmdsb 
    );
	

	
	//fifo
	wire full;
	wire empty;
	wire s_valid;
	wire s_ready;
	wire m_ready;
	wire m_valid;
	wire [7:0] fifo_to_pseudo;
	
	//pseudo
	wire [7:0] pt_red_p;
	wire [7:0] pt_green_p;
	wire [7:0] pt_blue_p;
	wire [7:0] dummy_pixel = 8'd0;
	
	//control & clocking
	wire [7:0] cc_output_data_r;
	wire [7:0] cc_output_data_g;
	wire [7:0] cc_output_data_b;
	
	//external
	wire [7:0] ext_red;
	wire [7:0] ext_green;
	wire [7:0] ext_blue;

	
	//misc clock signals
	wire clk_out;
	wire sys_clk;
	wire clk_to_fifo;
	wire cam_clk_buf;
	wire clk_to_pseudo;
	wire clk_to_ext;
	
	//flip-floops
	reg [7:0] temp_red;
	reg [7:0] temp_green;
	reg [7:0] temp_blue;
	
	reg [7:0] temp_red2;
	reg [7:0] temp_green2;
	reg [7:0] temp_blue2;
	
	reg [7:0] temp_fifo;
	
	wire [7:0] to_fifo_reg;
	wire [7:0] temp_to_temp_red;
	wire [7:0] temp_to_temp_green;
	wire [7:0] temp_to_temp_blue;
	
	wire [7:0] temp_to_temp_red2;
	wire [7:0] temp_to_temp_green2;
	wire [7:0] temp_to_temp_blue2;
	
	IBUFG ibufg1( .I(cam_clk),
						.O(cam_clk_buf));
	
						
	IBUFG ibufg2( .I(clk_in),
						.O(clk_out));
	
	clock_splitter split_it_2_quit_it(// Clock in ports
    .CLK_IN1(clk_out),      // IN
    .CLK_OUT1(sys_clk)     // OUT
	 );    
	 
	 /*
	 BUFG bufg1( .I(clk_out),
						.O(sys_clk));
						*/
	
	assign s_valid = frame_valid && line_valid;
	
	pixel_fifo cam_to_pseudo (
	  .wr_clk(cam_clk_buf), // input wr_clk
	  .rd_clk(sys_clk), // input rd_clk
	  .din(pixel_data), // input [7 : 0] din
	  .wr_en(s_valid), // input wr_en
	  .rd_en(m_ready), // input rd_en
	  .dout(to_fifo_reg), // output [7 : 0] dout
	  .full(full), // output full
	  .empty(empty) // output empty
	);
	
	 
	
	pseudo_thermal pseudo (
    .pixel_data(fifo_to_pseudo), 
    .clock(sys_clk), 
	 .empty(empty),
	 .ready(m_ready),
    .pt_red_p(pt_red_p), 
    .pt_green_p(pt_green_p), 
    .pt_blue_p(pt_blue_p)
    );
	 
	 
	 /*
	 yuv_to_rgb rgb (
    .pixel_data(fifo_to_pseudo), 
    .clock(sys_clk), 
    .empty(empty), 
    .ready(m_ready), 
    .pt_red_p(pt_red_p), 
    .pt_green_p(pt_green_p), 
    .pt_blue_p(pt_blue_p)
    );
	*/
	dvid_test external (
    .clk_in(clk_out), 
    .ext_red_p(ext_red), 
    .ext_green_p(ext_green), 
    .ext_blue_p(ext_blue), 
    .tmds(ext_tmds), 
    .tmdsb(ext_tmdsb)
    );
	
	assign fifo_to_pseudo = temp_fifo;
	
	assign temp_to_temp_red = temp_red;
	assign temp_to_temp_green = temp_green;
	assign temp_to_temp_blue = temp_blue;
	
	assign ext_red = temp_red2;
	assign ext_green = temp_green2;
	assign ext_blue = temp_blue2;
	
	always @(posedge sys_clk) begin
		temp_fifo <= to_fifo_reg;
		
		temp_red <= pt_red_p;
		temp_green <= pt_green_p;
		temp_blue <= pt_blue_p;
		
		temp_red2 <= temp_to_temp_red;
		temp_green2 <= temp_to_temp_green;
		temp_blue2 <= temp_to_temp_blue;
		
		
	end

endmodule
